Preview of IEDM Presentations at Stanford: 9am-12pm on Dec. 7th, Fri @Packard 202

Preview of IEDM Presentations at Stanford

Date: December 7th, 2012 (Friday)
Time: 9am-12pm
Place: Packard 202
Host: Prof. H.-S. Philip Wong

1. 9:00 am

10.4 A Neuromorphic Visual System Using RRAM Synaptic Devices with Sub-pJ Energy and Tolerance to Variability: Experimental Characterization and Large-Scale Modeling,  S. Yu, B. Gao, Z. Fang***, H. Yu**, J. Kang*, H.-S. P. Wong, Stanford University, *Peking University, **South University of Science and Technology, ***A*STAR

We report metal oxide resistive switching memory (RRAM) as synaptic devices for a neuromorphic visual system. At the device level, we experimentally characterized the gradual resistance modulation of RRAM by hundreds of identical pulses and a low energy consumption (<1 pJ per spike). At the system level, we simulated the performance of image orientation selectivity on a neuromorphic visual system which consists of CMOS neuron circuits and a 16 kb RRAM array. It was found that the system can tolerate the variability which is commonly present in RRAM devices.

2. 9:30 am

20.5 Electrode/Oxide Interface Engineering by Inserting Single-Layer Graphene: Application for HfOx–Based Resistive Random Access Memory, H.-Y. Chen, H. Tian*, B. Gao, S. Yu, J. Liang, J. Kang***, Y. Zhang**, T.-L. Ren*, H.-S. P. Wong, Stanford University, *Tsinghua University, **Lawrence Berkeley National Laboratory, ***Peking University

In this paper, electrode/oxide interface with inserted single-layer graphene (SLG) is studied using Ramen spectroscopy and electrical measurement. Raman mapping and single point measurements show noticeable changes in both D-band and G-band signal of SLG during the electrical cycling. This might suggest a new methodology to investigate the migration of oxygen ions in metal oxide resistive random access memory (RRAM). Applying this interface engineering technique to HfOx-based RRAM, the SLG increases low resistance state (LRS) resistance (> 1MΩ) due to its intrinsically high out-of-plane resistance. This enables the reduction of RESET current by 22X and programming power consumption by 47X. This work indicates that interface engineering design plays an important role in addition to exploring different metal oxides or metal electrode materials for RRAM.

3. 10:00 am

14.6 State-of-the-art Graphene Transistors on Hexagonal Boron Nitride, High-k, and Polymeric Films for GHz Flexible Analog Nanoelectronics, J. Lee, K. Parrish, F. Chowdhury, T.-J. Ha, Y. Hao, L. Tao, A. Dodabalapur, R. Ruoff, D. Akinwande, University of Texas, Austin

We report state-of-the-art graphene transistors for flexible nanoelectronics with record current density, intrinsic gain, extrinsic frequency metrics, and the highest doubler conversion gain and power. In addition, current saturation, and robust electrical stability down to a record 0.7mm bending radius, and immersion in liquids were demonstrated for the first time.

4. 10:30 am

24.7 Exceeding Nernst Limit (59mV/pH): CMOS-Based pH Sensor for Autonomous Applications, K. Parizi, A. Yeh, A. Poon, H.S.P. Wong, Stanford University

A highly sensitive and accurate field-effect sensor was obtained in a standard differential pair CMOS structure without Ag/AgCl reference electrode. The device is composed of two sensors each with a floating gate (FG) field effect transistor (FET), a control gate (CG) and an extended sensing gate (SG). By extending the sensing gate and engineering the capacitance value of the CG, we achieved a remarkable sensitivity of 130mV/pH for our pH sensor exceeding the fundamental Nernst limit, 59mV/pH. In addition, we removed the bulky Ag/AgCl reference electrode by a novel technique employing differential measurement to cancel the effect of the common abnormal potential change occurs in the solution.

5. 11:00 am

26.1 Understanding Metal Oxide RRAM Current Overshoot and Reliability Using Kinetic Monte Carlo Simulation, S. Yu, X. Guan, H.-S.P. Wong, Stanford University

A Kinetic Monte Carlo simulator is developed for metal oxide resistive random access memory (RRAM) to study a full set of RRAM characteristics such as set/forming current overshoot, endurance, and retention. The simulations suggest that 1) eliminating the forming process and decreasing the parasitic capacitance is required for minimizing the overshoot effect and reducing the reset power consumption; 2) the degradation of endurance is mainly due to oxygen escaping from the electrode during cycling; 3) the oxygen migration barrier can be extracted from the retention baking test over a suitable temperature range.

6. 11:30

20.7 HfOx Based Vertical Resistive Random Access Memory for Cost-Effective 3D Cross-Point Architecture without Cell Selector, H.-Y. Chen, S. Yu, B. Gao, P. Huang*, J. Kang*, H.-S.P. Wong, Stanford University, *Peking University

Double-layer stacked HfOx vertical RRAM is demonstrated for 3D cross-point architecture using a cost-effective fabrication process. Electrode/oxide interface engineering using TiON layer results in non-linear I-V suitable for the selector-less array. The fabricated HfOx vertical RRAM shows excellent performances such as reset current (<50μA), switching speed (~50ns), switching endurance (>108 cycles), half-selected disturbance immunity (>109 cycles), retention (>105s @125oC). Moreover, a unique write/read scheme is proposed for 3D cross-point architecture, and the simulation shows that ~1Mb array without cell selector is achievable.